Obiettivi formativi
The aim of the second module is to provide the theoretical basis and the practical skills required to design embedded hardware and firmware compliant with industrial standards (safety, interoperability, maintainability). In addition, model-based design and automatic code generation using Matlab/Simulink will be considered.
Prerequisiti
Fondamenti di elettronica, fondamenti di programmazione.
Contenuti dell'insegnamento
Embedded hardware and firmware design in compliance with industrial and safety standards, model-based design.
Programma esteso
Embedded hardware for compliant systems (1 hr)
Sensing, control, actuation, redundancy, power supply, insulation.
Structured approach to firmware design (2 hr)
V-model, levels of abstraction, validation, verification, documentation.
Implementation: the building system (4 hr)
Source code, preprocessor, compiler, assembly language, machine code, internal operation of the CPU, registers, stack, assembler, linker, optimization.
Software testing and documentation (2 hr)
Unit testing, static and dynamic code analysis, code coverage, process documentation, inline documentation, Doxygen, authoring tools.
Version control systems (2 hr)
Concurrent development, centralized vs. distributed VCSs, SVN, GIT, repositories, update, commit, branching, tagging, merging.
Standards (1 hr)
Standardization organizations, operation, stage codes.
Safety standards (2 hr)
Introduction to safety standards, safety integrity levels, good programming practices.
Coding standards (2 hr)
Motivation, MISRA C, CERT C, Barr Group, rule examples.
Communication protocols (2 hr)
CAN, CANopen, J1939, introduction to industrial communication protocols.
Fixed point ALUs (5 hr)
Fixed point numeric formats, fixed point arithmetic, normalized fractional format, calculations with normalized quantities, examples (Ohm’s law, magnetic flux observer for IMs), TDL calculation structures, µC vs. DSP, fixed point numeric saturation.
Real time computation (2 hr)
Numerical approximation of functions and differential calculus, optimization.
Bootloaders (1 hr)
MCU vs. FPGA and SoC, MCU booting sequence, interrupt vector table relocation, OpenBLT.
Watchdogs (1 hr)
Timeout watchdog, windowed watchdog, hardware watchdog, independence, best practices.
Memory management and protection (1 hr)
Paging, alignment, MMU/MPU, virtual memory, error checking and management.
Model-based design (2 hr)
Automatic code generation, model-in-the-loop, software-in-the-loop, processor-in-the-loop, rapid control prototyping.
Bibliografia
Dispense del docente, standard e normative, documentazione dei tool software utilizzati.
